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5 – Operation
Standard Memory Address Map
Core1553BRT requires an external 2,048×16 memory device. This memory is split into sixty-four 32-
word data buffers. Each of the 30 subaddresses has a receive and a transmit buffer, as shown in
The memory allocated to the unused receive subaddresses 0 and 31 is used to provide status
information back to the rest of the system. At the end of every transfer, a transfer status word is written to
these locations.
Table 5-1 ? Standard Memory Address Map
Address
000–01F
020–03F
...
RAM Contents
RX transfer status words
Receive subaddress 1
...
Action
The core only writes to these addresses (except when
SA30LOOP is HIGH).
3C0–3DF Receive subaddress 30
3E0–3FF
TX transfer status words
400–41F
420–43F
...
Not used
TX transfer subaddress 1
...
The core only reads from these addresses.
7C0–7DF TX transfer subaddress 30
7E0–7FF
Not used
If the SA30LOOP input is set HIGH, the RT maps transmit subaddress 30 to receive subaddress 30; i.e.,
the upper address bit is forced to 0. This provides a loopback subaddress, as per MIL-STD-1553B,
Notice 2. The TSW is still written to address 03FE. It should be noted that this is not strictly compliant
with the specification, since the transmit buffer will contain invalid data if the received command fails,
e.g., with a parity error. The transmit buffer should only be updated if the receive command had no errors.
To implement this function in full compliance, the SA30LOOP input should be tied LOW, and the RT
backend should copy the receive memory buffer to the transmit memory buffer only after the RT signals
that the message was received with no errors.
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